1. Field of the Invention
The present invention relates to a semiconductor apparatus and a method of disposing an observation flip-flop. Particularly, the present invention relates to a semiconductor apparatus and a method of disposing an observation flip-flop which suppress an increase in line capacitance due to the addition of an observation flip-flop.
2. Description of Related Art
A circuit of a semiconductor apparatus is recently increasing in size. A semiconductor apparatus usually undergoes a short-circuit test of a signal line in the apparatus. However, as a circuit size increases, a connection of signal lines in an internal circuit becomes complex, which makes it unable to keep track of the state of signal lines in an internal circuit through an external terminal of the semiconductor apparatus. To address this, recent semiconductor apparatus employ a scan chain circuit, which is composed of observation flip-flops connected in series, as a test circuit to keep track of the state of signal lines upon delivery inspection. A technique that uses such a scan chain circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2006-58273, which is referred to hereinafter as the related art.
FIG. 7 is a circuit diagram of a semiconductor apparatus 100 which is disclosed in the related art. As shown in FIG. 7, the semiconductor apparatus 100 includes input/output terminals 101A and 101B, a combinational circuit 102, observation flip-flops 1031 to 103m+n, and selectors 104 to 109. In the semiconductor apparatus 100, the state of signal lines in the combinational circuit 102 is captured by the observation flip-flops 1031 to 103m+n. The captured data is output from the input/output terminals 101A and 101B. In the semiconductor apparatus 100, a scan chain circuit is divided into a scan chain circuit which is composed of the observation flip-flops 1031 to 103m and a scan chain circuit which is composed of the observation flip-flops 103m+1 to 103m+n, thereby reducing the length of each scan chain circuit. It is thereby possible to reduce the number of clocks required from data capture to data output and also reduce a time period required from data capture to data output.
In the semiconductor apparatus, an observation flip-flop is generally disposed in a free space within a chip. Thus, an observation flip-flop may be placed in a position away from a signal line whose state is to be observed. If an observation flip-flop and a signal line to be observed are connected through a long line, parasitic capacitance of the line is added to parasitic capacitance of the signal line to be observed. The parasitic capacitance of a signal line to be observed thereby increases due to the insertion of an observation flip-flop.
Recent semiconductor apparatus have a low operating power supply voltage to achieve lower power consumption. A decrease in operating power supply voltage generally leads to a decrease in current supply capacity of elements that form an internal circuit. If large capacitance is connected to the output of those elements in such a condition, the delay of an output signal increases. In short, the placement of an observation flip-flop, which is added to improve the reliability of a semiconductor apparatus, causes an increase in parasitic capacitance of a signal line, which leads to an increase in signal delay in an internal circuit. This can cause malfunction of the semiconductor apparatus.